The present application is related generally to a digital device architecture and, more particularly, to a digital system configuration and associated method for devices including an electromechanical data Storage Element. The invention is particularly well suited for use in a portable device.
One need only briefly survey virtually any public area in modern society in order to gain an appreciation for the popularity of electronic devices. Such devices include, but are not limited to cellular phones, music players, portable computers, personal digital assistants, pagers, digital cameras, digital camcorders, personal gaming devices and e-books. Continuous improvement has been seen in the capabilities present in these devices attributable, at least in part, to a movement into digital implementations.
Demands, with regard to future electronic devices, include further miniaturization coupled with still further improvements in performance. These demands are markedly intense with regard to portable devices. A particular area of concern resides in a desire to store ever-increasing amounts of digital information. At the same time, it should be appreciated that an electronic device, especially in a portable or miniaturized form, is likely to be subjected to a somewhat harsh environment, particularly with regard to mechanical shock. In an attempt to cope with the need for a significant amount of digital data storage while, at the same time, dealing with the problem of mechanical shock, designers resorted to the use of electronic memory, particularly in the form of flash memory. This solution is evident in the instance of state-of-the-art music players, including MP3 players. As of this writing, the popular configuration of these players is to use a removable flash memory card having a size of approximately 32 MB. Unfortunately, several problems are associated with this solution, as will be described.
One problem seen with regard to the flash memory solution resides in the fact that 32 MB is, in itself, a somewhat limited amount of storage. It is not unforeseeable that in the near future even amounts less than 512 MB will be considered as small. Considering present day devices, the owner of a portable device that relies on the use of flash memory cards typically must own a number of the cards in order to provide a sufficient overall amount of storage. Otherwise, the portable device owner may be forced to frequently reload the flash memory card via a personal computer or otherwise be subjected, for example, to listening to a quite limited music selection in the instance of an MP3 player. Moreover, the cost of flash memory cards is currently somewhat prohibitive. Many portable device owners simply choose not to incur the expense of buying numbers of additional flash memory cards.
In coping with the problems inherent in the use of flash memory cards, a recent alternative solution has been the provision of a larger, electromechanical digital storage arrangement that is nonetheless removable. This solution is exemplified by the IBM Microdrive™. The latter is a removable miniaturized computer hard disk drive provided with a connector that mates with a corresponding connector incorporated within the portable device to be served. It is noted that such miniature hard drives, including the Microdrive, have essentially the same configuration as prior art hard drives seen in personal computers. That is, the miniature hard drive is made up of two general assemblies including a head disk assembly (HDA) and a printed circuit board assembly (PCBA). The HDA itself includes a rotatable magnetic media, a sensor assembly for reading from and writing to the rotatable media and motors for accomplishing rotation of the rotatable media and positioning of the sensor assembly. The PCBA includes essentially all of the electronics needed to operate the HDA with the common exception of a preamplifier. While the Microdrive brings improvement in data capacity, as of this writing, the cost of the Microdrive is quite high in terms of megabytes per dollar and absolute cost when compared to such costs in conventional drives. It is submitted that this absolute cost, in and by itself, will prove to be a significant barrier with regard to broad-based use of the product.
The Microdrive utilizes a CompactFlash interface. This interface raises concerns for a number of reasons, not the least of which is the requirement for a rather bulky interface connector having fifty pins, as described in the CF+ and CompactFlash Specification Revision 1.4. Further concerns with regard to CompactFlash will be addressed below.
With regard to the removable configuration of the Microdrive, it is noted that the perceived need for removable media has been greatly reduced in certain environments once viable, significant levels of “permanently” installed storage space has been provided. Available embedded storage has traditionally taken a precedent over removable storage, as evidenced in desktop computers. Still further concerns are associated with removable storage, as will be discussed below.
While the use of a miniaturized hard disk drive effectively resolves the problem of limited storage by providing many times the storage currently available in a typical flash memory card, the issue of the use of such a component in the potentially harsh environment of a portable device is once again brought to the forefront. It should be appreciated that, under certain circumstances, prior art hard disk drives tolerate relatively high levels of mechanical shock—even as high as 1500 Gs. Under operational circumstances, unfortunately, hard disk drives are generally quite susceptible to mechanical shock events, for example, during the time that the head or sensing assembly is actually accessing the rotating media. Consequences of a mechanical shock event occurring at precisely the most inopportune time include potential drive failure. For instance, a drive may fail when subjected to a 175 G event during an access. In this regard, Applicants are unaware of a miniaturized hard drive or overall device architecture incorporating effective features specifically intended to cope, for example, with the potentially harsh environment of a portable electronic device.
U.S. Pat. No. 6,061,751 (hereinafter the '751 patent), sharing the lead inventor of the present application, serves as one reference point with regard to several suggestions which may be utilized within a system incorporating a hard drive. The framework of the '751 patent, however, resides not in the area of drive miniaturization, ruggedization or portability, but primarily in reducing the cost of a hard disk drive as provided in an overall computer system. One approach taken by the patent encompasses moving all possible functionality out of the overall hard disk drive, including the controller, and onto the motherboard of the host device. For example, unused silicon “real estate” might be utilized for implementation of the controller. Moreover, such a controller may utilize memory that is already present on the host side. Thus, the drive cost is reduced to some extent. At the same time, it should be appreciated that the prior art functional control implemented as between the CPU and the controller is unchanged with respect to locating the controller on the motherboard. Specifically, the controller includes processing power which executes control code that is “native” to the peripheral device. As used herein, “native code” refers to the lowest level control code required to control a particular peripheral device. It is that code which is customarily executed by a device controller in a fashion that is isolated from the CPU resident within the host system.
FIG. 1 is a representation of FIG. 2 of the '751 patent, including alternative reference numbers assigned consistent with the present discussion. Accordingly, a prior art computer system 10 includes a host circuit board 12. A controller 14 is included as a single integrated circuit having further functions, as will be mentioned. A servo integrated circuit 16 is used to spin motors in any attached peripheral devices. Three peripheral devices are shown including a head disk assembly (HDA) 20, a CDROM/DVD 22 and a floppy drive 24. Alternatively, the latter may comprise a high capacity floppy drive, a miniature drive, or other suitable device.
One advantage, alluded to above, in the patent is the use of the HDA as an alternative to a complete hard disk drive (HDD) since costs are lessened by including components such as, for example, controller 14 within the host system. Components of the HDA (described above, but not illustrated) include a data media, a sensor/head mechanism to read and/or write data to and from the media, and motors to spin the media and position the sensor/head mechanism. A preamplifier is included to amplify the data read from or to be written to the media. The preamplifier may be installed on a flex circuit (see item 17 in FIG. 1A of the '751 patent) that electrically connects the HDA to the PCBA. It is appropriate to note, at this juncture, that the '751 patent also describes the location of a read/write channel, electrically in communication with the preamplifier, as potentially being arranged in the host system, distributed between the host system and the peripheral device or being within the peripheral device. The conventional location of the read/write channel in prior art HDD's is on the PCBA in close physical proximity to the electrical connection point of the HDA, for reasons described below.
Continuing with a description of FIG. 1, each peripheral device may also have an associated personality ROM 26. The specific location of the personality ROM is shown for an individual component in FIG. 3 (item 64) of the '751 patent. It is noted that the personality ROM is isolated from the rest of the individual component and is accessed via the PCI arrangement. It is important to understand that the personality ROM contains information which may define characteristics of controller firmware that is required to operate a particular component (see the table beginning in cols. 7 and 8 of the patent), however, the disclosure presents no way in which to update the firmware with code provided from the personality ROM. As an example, if the host system in the '751 patent is to operate four different types of HDA, each of which requires completely different firmware, four sets of different firmware must be stored in the host device. As will be discussed below, the present invention considers this approach as unacceptable, at least for the reason that a great deal of storage space is required as a tradeoff for flexibility. Integrated circuit 14, in FIG. 1, further includes peripheral component interconnect (PCI) bus functionality such that the integrated circuit is interfaced to a PCI bus 28. It is noted that PCI bus 28 comprises one example of a number of possible bus mastering buses. A CPU 30 and chipset 32 are provided with the chipset connected to PCI bus 28. CPU 30 is, in turn, interfaced with chipset 32. A RAM section 34 is also interfaced to chipset 32. It is important to note that CPU 30 is indirectly connected to the peripheral components. Specifically, PCI bus 28 is interposed between the peripheral components, including HDA 26, and the CPU. While this arrangement may be advantageous with regard to cost reduction, certain disadvantages that accompany this configuration will be considered at appropriate points below. For the moment, it is noted that system control is accomplished by the CPU issuing commands that are placed on PCI bus 28 in accordance with mandated PCI protocol. It is submitted that certain penalties are associated with this style of command configuration. For example, commands issued through levels or layers of protocol higher than the native code are particularly inflexible.
Attention is now directed to FIG. 21, which illustrates a prior art computer system that is generally indicated by the reference numeral 50. System 50 includes a conventional HDD 52 that is connected to a host computer 54 by a parallel interface arrangement 56 such as, for example, an IDE or SCSI interface. Only selected electronic components of HDD 52 have been illustrated for purposes of clarity, however, it is to be understood that these electronic components are connected in a conventional manner with their typical electromechanical counterparts, as will be understood by one having ordinary skill in the art. The electronic components of HDD 52 include a servo IC 58, a read/write IC 60 and a preamp IC 62. Further, a controller IC 64 is individually interfaced with each of the servo IC, read/write IC and preamp IC. While the present figure illustrates one prior art configuration, there have been a number of modifications in the individual interfaces with ICs that are serviced by controller 64. As one example, functionality has been moved from the controller IC into servo IC 58 in a way which eliminates the Zero-Crossing and Commutate lines. As another example, servo IC 58 and Read/Write IC 60 can share a serial clock line and a serial data line, however, each IC is provided with a unique enable line.
Still referring to FIG. 21, controller 64 is also externally connected with interface arrangement 56 for communication with host computer 54. Individual signals that are present within the interfaces between controller IC 64 have been labeled in the figure, but will not be described in detail since these signals will be familiar to one having ordinary skill in the art. For present purposes, it is important to understand, however, that each of the servo IC, the read/write IC and the preamp IC includes a dedicated serial interface indicated by the reference numbers 70, 72 and 74, respectively, that is connected to controller IC 64 for control purposes. Each serial IC interface includes a dedicated serial port enable line, a dedicated serial port clock line and a dedicated serial port data line. Accordingly, controller IC 64 must include individual serial interfaces that are adapted for each of the individual ICs which the controller services. Share serial port data and serial port clock but with unique enable signals.
In addition to each serial device requiring a dedicated serial interface and port, each serial device is configured to operate responsive to a particular, customized command set that is often quite unlike the command sets that are associated with other serial devices that are present. Often, commands, as well as device responses thereto, are issued utilizing internal registers within each serial device. In order to access one of these internal registers, a command must include some sort of address field, identifying the internal register, and may include a data field. The response to the command may comprise a response data field. Unfortunately, there is no standardization from device to device with respect to the registers used, the command set, the address field length or data field length. In the general context of the prior art, this configuration has not been a concern since the controller is co-located with the serial devices. While the '751 patent moves the controller to the host device, PCI mass storage IC 14 is provided to cope with disk data transfer issues, rather than serial control-related data issues. The patent appears to leave the serial control-related data issue in a still further complicated state, as is particularly evidenced with regard to the servo IC. Specifically, FIG. 3 of the '751 patent shows the servo IC in the host device and merely extends the drive interface between the servo IC and the servo motor such that individual, “analog” drive signals for each coil of the motor are present in the interface. The present invention considers this approach as unacceptable at least for the reason that the number of signals present in the interface is unduly multiplied.
With continuing reference to FIG. 21, traditional disk drives, as well as other forms of data storage devices, contain a control arrangement such as controller IC 64. This IC traditionally provides all of the control functions for the disk drive including, but not limited to:                Receiving, interpreting, and executing commands from the host system;        Operating and controlling the spindle motor system, using Servo IC 58 in the present example;        Operating and controlling the VCM/Actuator (again, using Servo IC 58);        Managing writes and reads of data to/from the disk by controlling other ICs such as Preamp IC 62 and Read/Write IC 60; and        Detecting various error conditions, as well as executing recovery algorithms, if appropriate.        
While the traditional controller IC includes many circuits to assist in these functions, much of the functionality is optimally implemented in firmware algorithms. This firmware is traditionally large and complex in order to provide all the required functionality.
The firmware is traditionally stored on a separate IC (not shown) from the Controller/Processor IC within the drive. This IC is usually some type of programmable ROM device such as one-time-programmable ROM, Flash, EEPROM or other suitable device. Such programmable electronic devices as these are typically used because the firmware for a disk drive or any data storage device, for that matter, often must be revised and/or improved frequently as the product evolves. These changes are usually to improve manufacturing yields, operational reliability or to add new functionality, all of which improve the cost or competitive advantage of the product. The firmware change being described here is not so much a field upgrade, but a revision to the firmware incorporated in the product at the time of manufacture.
The frequency of firmware changes is typically highest during early product introduction and manufacturing (early in the product's life cycle). As a product continues to be manufactured over time, the firmware is often stabilized and, as a cost reduction, the programmable ROM parts mentioned above are changed to either one-time-only programmable parts or mask-programmed parts. The point being that, early in a product's life cycle, it is necessary to have a design which allows for rapid revision of the firmware placed onto the product during manufacture so that problems can be resolved, yields improved and the like.
The prior art has developed a number of approaches in coping with these concerns. For example, as time and experience accumulate on a family of products, the firmware becomes stable. When, at some point a new product is introduced, the firmware can include a “core” set of firmware that is based on stable firmware for the family of products from which the new product was derived. This stable core of firmware can be implemented in masked ROM which is incorporated into the controller IC. This core firmware is, ideally, functional, reliable and able to operate the product to a level which enables additional firmware (for full product functionality) to be read from the disk into RAM memory may also be co-located on in the controller IC. This additional firmware can be easily revised and written onto the disk at the time of manufacture. Accordingly, this prior art solution eliminates the need for a separate ROM device, thereby reducing cost and providing for revisions of the additional firmware which is located on the disk. It is important to recognize, however, that a very stable/reliable “core” firmware must be available. Thus, this prior art approach is not well suited for a completely new product/technology introduction.
In view of the foregoing, it would be desirable to provide a new approach allowing for flexible firmware development, particularly in new, early generation product lines.
The present invention provides a highly advantageous digital device configuration and method that are submitted to resolve the foregoing problems and concerns while providing still further advantages, as described hereinafter.